21 #include <sys/types.h>
28 #define RTE_PCI_CFG_SPACE_SIZE 256
29 #define RTE_PCI_CFG_SPACE_EXP_SIZE 4096
31 #define RTE_PCI_STD_HEADER_SIZEOF 64
34 #define RTE_PCI_VENDOR_ID 0x00
35 #define RTE_PCI_DEVICE_ID 0x02
36 #define RTE_PCI_COMMAND 0x04
37 #define RTE_PCI_STATUS 0x06
38 #define RTE_PCI_BASE_ADDRESS_0 0x10
39 #define RTE_PCI_CAPABILITY_LIST 0x34
42 #define RTE_PCI_COMMAND_MEMORY 0x2
43 #define RTE_PCI_COMMAND_MASTER 0x4
44 #define RTE_PCI_COMMAND_INTX_DISABLE 0x400
47 #define RTE_PCI_STATUS_CAP_LIST 0x10
50 #define RTE_PCI_BASE_ADDRESS_SPACE_IO 0x01
53 #define RTE_PCI_CAP_ID_PM 0x01
54 #define RTE_PCI_CAP_ID_MSI 0x05
55 #define RTE_PCI_CAP_ID_VNDR 0x09
56 #define RTE_PCI_CAP_ID_EXP 0x10
57 #define RTE_PCI_CAP_ID_MSIX 0x11
58 #define RTE_PCI_CAP_SIZEOF 4
59 #define RTE_PCI_CAP_NEXT 1
62 #define RTE_PCI_PM_CTRL 4
63 #define RTE_PCI_PM_CTRL_STATE_MASK 0x0003
64 #define RTE_PCI_PM_CTRL_PME_ENABLE 0x0100
65 #define RTE_PCI_PM_CTRL_PME_STATUS 0x8000
68 #define RTE_PCI_EXP_TYPE_RC_EC 0xa
69 #define RTE_PCI_EXP_DEVCTL 0x08
70 #define RTE_PCI_EXP_DEVCTL_PAYLOAD 0x00e0
71 #define RTE_PCI_EXP_DEVCTL_READRQ 0x7000
72 #define RTE_PCI_EXP_DEVCTL_BCR_FLR 0x8000
73 #define RTE_PCI_EXP_DEVSTA 0x0a
74 #define RTE_PCI_EXP_DEVSTA_TRPND 0x0020
75 #define RTE_PCI_EXP_LNKCTL 0x10
76 #define RTE_PCI_EXP_LNKSTA 0x12
77 #define RTE_PCI_EXP_LNKSTA_CLS 0x000f
78 #define RTE_PCI_EXP_LNKSTA_NLW 0x03f0
79 #define RTE_PCI_EXP_SLTCTL 0x18
80 #define RTE_PCI_EXP_RTCTL 0x1c
81 #define RTE_PCI_EXP_DEVCTL2 0x28
82 #define RTE_PCI_EXP_LNKCTL2 0x30
83 #define RTE_PCI_EXP_SLTCTL2 0x38
86 #define RTE_PCI_MSIX_FLAGS 2
87 #define RTE_PCI_MSIX_FLAGS_QSIZE 0x07ff
88 #define RTE_PCI_MSIX_FLAGS_MASKALL 0x4000
89 #define RTE_PCI_MSIX_FLAGS_ENABLE 0x8000
91 #define RTE_PCI_MSIX_TABLE 4
92 #define RTE_PCI_MSIX_TABLE_BIR 0x00000007
93 #define RTE_PCI_MSIX_TABLE_OFFSET 0xfffffff8
96 #define RTE_PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
97 #define RTE_PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
99 #define RTE_PCI_EXT_CAP_ID_ERR 0x01
100 #define RTE_PCI_EXT_CAP_ID_DSN 0x03
101 #define RTE_PCI_EXT_CAP_ID_ACS 0x0d
102 #define RTE_PCI_EXT_CAP_ID_SRIOV 0x10
103 #define RTE_PCI_EXT_CAP_ID_PRI 0x13
104 #define RTE_PCI_EXT_CAP_ID_PASID 0x1b
107 #define RTE_PCI_ERR_UNCOR_STATUS 0x04
108 #define RTE_PCI_ERR_COR_STATUS 0x10
109 #define RTE_PCI_ERR_ROOT_STATUS 0x30
112 #define RTE_PCI_ACS_CAP 0x04
113 #define RTE_PCI_ACS_CTRL 0x06
114 #define RTE_PCI_ACS_SV 0x0001
115 #define RTE_PCI_ACS_RR 0x0004
116 #define RTE_PCI_ACS_CR 0x0008
117 #define RTE_PCI_ACS_UF 0x0010
118 #define RTE_PCI_ACS_EC 0x0020
121 #define RTE_PCI_SRIOV_CAP 0x04
122 #define RTE_PCI_SRIOV_CTRL 0x08
123 #define RTE_PCI_SRIOV_INITIAL_VF 0x0c
124 #define RTE_PCI_SRIOV_TOTAL_VF 0x0e
125 #define RTE_PCI_SRIOV_NUM_VF 0x10
126 #define RTE_PCI_SRIOV_FUNC_LINK 0x12
127 #define RTE_PCI_SRIOV_VF_OFFSET 0x14
128 #define RTE_PCI_SRIOV_VF_STRIDE 0x16
129 #define RTE_PCI_SRIOV_VF_DID 0x1a
130 #define RTE_PCI_SRIOV_SUP_PGSIZE 0x1c
133 #define RTE_PCI_PRI_CTRL 0x04
134 #define RTE_PCI_PRI_CTRL_ENABLE 0x0001
135 #define RTE_PCI_PRI_ALLOC_REQ 0x0c
138 #define RTE_PCI_PASID_CTRL 0x06
141 #define PCI_PRI_FMT "%.4" PRIx32 ":%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8
142 #define PCI_PRI_STR_SIZE sizeof("XXXXXXXX:XX:XX.X")
145 #define PCI_SHORT_PRI_FMT "%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8
148 #define PCI_FMT_NVAL 4
151 #define PCI_RESOURCE_FMT_NVAL 3
154 #define PCI_MAX_RESOURCE 6
179 #define RTE_PCI_ANY_ID (0xffff)
181 #define PCI_ANY_ID RTE_DEPRECATED(PCI_ANY_ID) RTE_PCI_ANY_ID
182 #define RTE_CLASS_ANY_ID (0xffffff)
196 char *output,
size_t size);
void rte_pci_device_name(const struct rte_pci_addr *addr, char *output, size_t size)
int rte_pci_addr_cmp(const struct rte_pci_addr *addr, const struct rte_pci_addr *addr2)
int rte_pci_addr_parse(const char *str, struct rte_pci_addr *addr)
uint16_t subsystem_vendor_id
uint16_t subsystem_device_id